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I designed a system to generate SHA256 hash codes using Altera Cyclone III FPGA.

Design is done using Quartus II software provided by Altera And Verilog HDL.

 

I finished this project using two kinds of architecture:

1- First one is done using the internal registers of FPGA. This one has got around 9900 Logic Elements and you can fit it in an EP3C10E144A7 Cyclone III FPGA. Now I used a nice idea to reduce the clock cycles needed to only 40. It means that if your message is 512 bits you can get it's SHA256 after only 40 clock pulses, if your message is 2*512 bits you get your answer after 80 clock pulses and so on.

2- The second one is done using internal M9K RAM memories of the FPGA. This one is much slower but more reliable. Because it uses only 1400 Logic Elements and 8200 bits of RAM. It means that you can easily fit 6 parallel SHA256 computers in the same Cyclone III FPGA I mentioned above.

In the following schematic you can see the architecture using the block RAMs :

SHA256 Generator Schematic 

Ok if you need the Quartus source files you can contact me through my Email or the Contact section of web site. See you...

   

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